[{"data":1,"prerenderedAt":4},["ShallowReactive",2],{"OfiLpYZJDu":3},"# circuitlib\n\nA circuit verification library for Lean4.\n\n[Documentation](https://matt.hunzinger.me/circuitlib/docs)\n\n## Roadmap\n\n### Circuits\n\n#### Combinational\n\n- Logic Gates\n  - [x] AND Gate\n  - [x] OR Gate\n  - [x] NOT Gate\n  - [x] NAND Gate\n  - [x] NOR Gate\n  - [x] XOR Gate\n  - [x] XNOR Gate\n- Arithmetic Circuits\n  - [x] Half Adder\n  - [x] Full Adder\n  - [ ] Ripple Carry Adder\n  - [ ] Carry Lookahead Adder\n  - [ ] Half Subtractor\n  - [ ] Full Subtractor\n  - [ ] Multiplier\n- Data Routing\n  - [ ] Multiplexer (MUX)\n  - [ ] Demultiplexer (DEMUX)\n  - [ ] Encoder\n  - [ ] Decoder\n  - [ ] Priority Encoder\n- Comparison & Conversion\n  - [ ] Magnitude Comparator\n  - [ ] Binary to Gray Code Converter\n  - [ ] Gray to Binary Converter\n  - [ ] BCD to 7-Segment Decoder\n\n### Sequential\n\n- Latches\n  - [ ] SR Latch\n  - [ ] D Latch\n- Flip-Flops\n  - [ ] SR Flip-Flop\n  - [ ] D Flip-Flop\n  - [ ] JK Flip-Flop\n  - [ ] T Flip-Flop\n  - [ ] Master-Slave Flip-Flop\n- Registers\n  - [ ] Serial-In Serial-Out (SISO) Shift Register\n  - [ ] Serial-In Parallel-Out (SIPO) Shift Register\n  - [ ] Parallel-In Serial-Out (PISO) Shift Register\n  - [ ] Parallel-In Parallel-Out (PIPO) Shift Register\n  - [ ] Universal Shift Register\n- Counters\n  - [ ] Asynchronous (Ripple) Counter\n  - [ ] Synchronous Counter\n  - [ ] Up/Down Counter\n  - [ ] Mod-N Counter\n  - [ ] Ring Counter\n  - [ ] Johnson Counter\n- Memory\n  - [ ] ROM (Read-Only Memory)\n  - [ ] SRAM Cell\n  - [ ] FIFO Buffer\n\n### State Machines\n\n- [ ] Mealy Machine\n- [ ] Moore Machine\n\n## Usage\n\n`lakefile.toml`:\n\n```toml\n[[require]]\nname = \"circuitlib\"\nscope = \"matthunz\"\nrev = \"main\"\n```\n\n`lakefile.lean`:\n\n```lean4\nrequire circuitlib from git \"https://github.com/matthunz/circuitlib\" @ \"main\"\n```\n",1780113386883]